1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and more specifically to a method of forming a novel MOS transistor with deposited silicon regions.
2. Discussion of Related Art
Today literally millions of individual transistors are coupled together to form very large-scale integrated (VSLI) circuits, such as microprocessors, memories, and application specific integrated circuits (IC's). Presently, the most advanced IC's are made up of approximately three million transistors, such as metal oxide semiconductor (MOS) field effect transistors having gate lengths on the order of 0.25 .mu.m. In order to continue to increase the complexity and computational power of future integrated circuits, more transistors must be packed into a single IC (i.e., transistor density must increase). Thus, future ultra large-scale integrated (ULSI) circuits will require very short channel transistors with effective gate lengths less than 0.1 .mu.m. Unfortunately, the structure and method of fabrication of conventional MOS transistors cannot be simply "scaled down" to produce smaller transistors for higher density integration.
The structure of a conventional MOS transistor 100 is shown in FIG. 1. Transistor 100 comprises a gate electrode 102, typically polysilicon, formed on a gate dielectric layer 104 which in turn is formed on a silicon substrate 106. A pair of source/drain extensions or tip regions 110 are formed in the top surface of substrate 106 in alignment with outside edges of gate electrode 102. Tip regions 110 are typically formed by well-known ion implantation techniques and extend beneath gate electrode 102. Formed adjacent to opposite sides of gate electrode 102 and over tip regions 110 are a pair of sidewall spacers 108. A pair of source/drain contact regions 120 are then formed, by ion implantation, in substrate 106 substantially in alignment with the outside edges of sidewall spacers 108.
As device features are continually scaled down, the source/drain contact resistance negatively impacts device performance. In order to help reduce the contact resistance, deposited silicon can be formed on the source/drain contact regions 120 to generate raised source/drain regions and/or to form a sacrificial silicon film for a silicide process. Unfortunately, present techniques for selectively depositing silicon generally require high temperature hydrogen predeposition bakes at 900.degree. C. or higher for a period of a minute or longer. Such high temperature predeposition bakes increase the thermal energy seen by the devices which can cause an undesired redistribution of dopants. Additionally, present selective silicon deposition techniques are highly dependent upon the conductivity type of the silicon surface on which they are formed. As such, one is presently unable to selectively deposit a silicon film onto p-type and n-type silicon surfaces at the same time. Still further, present processing techniques are unable to uniformly deposit highly (&gt;5.times.10.sup.2 l atoms/cm.sup.3) insitu doped silicon films at a low temperatures and with a low thermal budget without discontinuities or faceting, making present deposition techniques incompatible with the formation of raised source/drain regions.
Thus, what is desired is a method of forming a selectively deposited, highly conductive insitu doped silicon or silicon alloy film at low temperatures and simultaneously onto both conductivity types of silicon surfaces.